Microarchitecture

TEA-RC: Thread Context-Aware Register Cache for GPUs

Ipoom Jeong, Yunho Oh, Won Woo Ro, Myung Kuk Yoon

CASINO Core Microarchitecture: Generating Out-of-Order Schedules Using Cascaded In-Order Scheduling Windows

In this work, we propose a CASINO core microarchitecture that dynamically and speculatively generates out-of-order instruction issue schedules with complexity close to in-order scheduling by leveraging CAScaded IN-Order scheduling windows.

Ipoom Jeong, Seihoon Park, Changmin Lee, Won Woo Ro

OverCome: Coarse-Grained Instruction Commit with Handover Register Renaming

In this paper, we propose an OverCome microarchitecture based on a history-based approach to augment the effective size of the instruction window via coarse-grained instruction commit.

Ipoom Jeong, Changmin Lee, Keunsoo Kim, Won Woo Ro

Constructing Resilient Region in Dynamic Optimization Systems via Dynamic Adjustment of Bias Thresholds

Performance of dynamic optimization system is strongly affected by the region it selects to optimize. Larger region has more …

Ipoom Jeong, Won Woo Ro

Parallel In-Order Execution Architecture for Low-Power Processor

Mobile devices, such as smartphones and tablet PCs, have been widely used in everyday life. These devices are required to provide high …

Kyungmin Lee, Ipoom Jeong, Won Woo Ro

Dynamic Warp Scheduler Selection Policy Using Linear Regression for GPUs

GPGPU has been popular in many research fields due to its ability to execute massive operations concurrently. Each and every emerging …

Hyunjun Shin, Kyungmin Lee, Ipoom Jeong, Jong Hyun Park, Won Woo Ro

Heterogeneous Core Microarchitecture with Functional Unit Gating for High Energy Efficiency

Energy efficiency has become an important issue in modern microprocessor designs. In this paper, we propose a core microarchitecture …

Yoonsoo Kim, Ipoom Jeong, Won Woo Ro

Exploiting Back-End Fusion in Multi-Core Processors

Jonghyun Park, Ipoom Jeong, Won Woo Ro