Microarchitecture

Warped-Compaction: Maximizing GPU Register File Bandwidth Utilization via Operand Compaction

Eunbi Jeong, Ipoom Jeong, Myung Kuk Yoon, Nam Sung Kim

Marching Page Walks: Batching and Concurrent Page Table Walks for Enhancing GPU Throughput

Jiwon Lee, Gun Ko, Myung Kuk Yoon, Ipoom Jeong, Yunho Oh, Won Woo Ro

Triple-A: Early Operand Collector Allocation for Maximizing GPU Register Bank Utilization

Recent GPUs provisioned with large register files cannot fully utilize the bandwidth between the register files and execution …

Ipoom Jeong, Eunbi Jeong, Nam Sung Kim, Myung Kuk Yoon

Triple-A: Early Operand Collector Allocation for Maximizing GPU Register Bank Utilization

CASH-RF: A Compiler-Assisted Hierarchical Register File in GPUs

Spin-transfer torque magnetic random-access memory (STT-MRAM) is an emerging nonvolatile memory technology that has been received …

Yunho Oh, Ipoom Jeong, Won Woo Ro, Myung Kuk Yoon

Reconstructing Out-of-Order Issue Queue

In this work, we propose an energy-efficient microarchitecture named Ballerino, carrying out BALanced and cache-miss toLERable dynamic scheduling via cascaded and clustered IN-Order IQs. The proposed microarchitecture is built upon three key principles that drive dynamic scheduling: instruction readiness, memory/register dependences, and oldest-first selection.

Ipoom Jeong, Jiwon Lee, Myung Kuk Yoon, Won Woo Ro

TEA-RC: Thread Context-Aware Register Cache for GPUs

Ipoom Jeong, Yunho Oh, Won Woo Ro, Myung Kuk Yoon

CASINO Core Microarchitecture: Generating Out-of-Order Schedules Using Cascaded In-Order Scheduling Windows

In this work, we propose a CASINO core microarchitecture that dynamically and speculatively generates out-of-order instruction issue schedules with complexity close to in-order scheduling by leveraging CAScaded IN-Order scheduling windows.

Ipoom Jeong, Seihoon Park, Changmin Lee, Won Woo Ro

OverCome: Coarse-Grained Instruction Commit with Handover Register Renaming

In this paper, we propose an OverCome microarchitecture based on a history-based approach to augment the effective size of the instruction window via coarse-grained instruction commit.

Ipoom Jeong, Changmin Lee, Keunsoo Kim, Won Woo Ro

Constructing Resilient Region in Dynamic Optimization Systems via Dynamic Adjustment of Bias Thresholds

Performance of dynamic optimization system is strongly affected by the region it selects to optimize. Larger region has more …

Ipoom Jeong, Won Woo Ro

Parallel In-Order Execution Architecture for Low-Power Processor

Mobile devices, such as smartphones and tablet PCs, have been widely used in everyday life. These devices are required to provide high …

Kyungmin Lee, Ipoom Jeong, Won Woo Ro