Microarchitecture

This work uncovers two previously unknown sources of Last-Level Cache (LLC) contention in Intel Xeon CPUs caused by high-bandwidth I/O devices and proposes A4, a runtime LLC management framework that mitigates these issues. A4 improves performance for latency-sensitive workloads by 51% without significantly affecting low-priority workloads.

The rapid advancements in CPU performance have slowed due to the end of Dennard scaling and the exponential growth of data, making it …

The GPU has been successfully used for diverse emerging compute-intensive applications, including imaging, computer vision, and more …

Virtual memory, with the support of address translation hardware, is a key technique in expanding programmability and memory management …

Recent GPUs provisioned with large register files cannot fully utilize the bandwidth between the register files and execution …

In this work, we set out to introduce the latest features supported by Intel DSA (Data Streaming Accelerator), deep-dive into its versatility, and analyze its throughput benefits through a comprehensive evaluation.

TBD

In this work, we set out to introduce the latest features supported by Intel DSA (Data Streaming Accelerator), deep-dive into its versatility, and analyze its throughput benefits through a comprehensive evaluation.

Spin-transfer torque magnetic random-access memory (STT-MRAM) is an emerging nonvolatile memory technology that has been received …

In this work, we propose an energy-efficient microarchitecture named Ballerino, carrying out BALanced and cache-miss toLERable dynamic scheduling via cascaded and clustered IN-Order IQs. The proposed microarchitecture is built upon three key principles that drive dynamic scheduling: instruction readiness, memory/register dependences, and oldest-first selection.