Microarchitecture

In modern server CPUs, the Last-Level Cache (LLC) serves not only as a victim cache for higher-level private caches but also as a …

The GPU has been successfully used for diverse emerging compute-intensive applications, including imaging, computer vision, and more …

Virtual memory, with the support of address translation hardware, is a key technique in expanding programmability and memory management …

Recent GPUs provisioned with large register files cannot fully utilize the bandwidth between the register files and execution …

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Spin-transfer torque magnetic random-access memory (STT-MRAM) is an emerging nonvolatile memory technology that has been received …

In this work, we propose an energy-efficient microarchitecture named Ballerino, carrying out BALanced and cache-miss toLERable dynamic scheduling via cascaded and clustered IN-Order IQs. The proposed microarchitecture is built upon three key principles that drive dynamic scheduling: instruction readiness, memory/register dependences, and oldest-first selection.

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In this work, we propose a CASINO core microarchitecture that dynamically and speculatively generates out-of-order instruction issue schedules with complexity close to in-order scheduling by leveraging CAScaded IN-Order scheduling windows.

In this paper, we propose an OverCome microarchitecture based on a history-based approach to augment the effective size of the instruction window via coarse-grained instruction commit.