Dynamic Scheduling

In this work, we propose an energy-efficient microarchitecture named Ballerino, carrying out BALanced and cache-miss toLERable dynamic scheduling via cascaded and clustered IN-Order IQs. The proposed microarchitecture is built upon three key principles that drive dynamic scheduling: instruction readiness, memory/register dependences, and oldest-first selection.

In this work, we propose a CASINO core microarchitecture that dynamically and speculatively generates out-of-order instruction issue schedules with complexity close to in-order scheduling by leveraging CAScaded IN-Order scheduling windows.

Mobile devices, such as smartphones and tablet PCs, have been widely used in everyday life. These devices are required to provide high …

Energy efficiency has become an important issue in modern microprocessor designs. In this paper, we propose a core microarchitecture …