CPU

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In this work, we evaluate true CXL-ready systems based on the latest 4th-generation Intel Xeon CPU with three CXL memory devices from different manufacturers, which divulges important differences between emulated and true CXL memory devices. Based on these observations, we propose a CXL-memory-aware dynamic page allocation policy, Caption, to use CXL memory more efficiently.

This paper presents LADIO (Leakage-Aware Direct I/O), an adaptive direct cache access mechanism (a.k.a., Data Direct I/O, DDIO) to alleviate the inter-I/O (between network I/O and storage I/O) interference problem in modern datacenter servers.

In this work, we propose an energy-efficient microarchitecture named Ballerino, carrying out BALanced and cache-miss toLERable dynamic scheduling via cascaded and clustered IN-Order IQs. The proposed microarchitecture is built upon three key principles that drive dynamic scheduling: instruction readiness, memory/register dependences, and oldest-first selection.

In this work, we propose a CASINO core microarchitecture that dynamically and speculatively generates out-of-order instruction issue schedules with complexity close to in-order scheduling by leveraging CAScaded IN-Order scheduling windows.

In this paper, we propose an OverCome microarchitecture based on a history-based approach to augment the effective size of the instruction window via coarse-grained instruction commit.

Performance of dynamic optimization system is strongly affected by the region it selects to optimize. Larger region has more …

Mobile devices, such as smartphones and tablet PCs, have been widely used in everyday life. These devices are required to provide high …

This paper analyzes various multi-core architectures that have been proposed for decades to increase the performance or power …