Parallel In-Order Execution Architecture for Low-Power Processor


Mobile devices, such as smartphones and tablet PCs, have been widely used in everyday life. These devices are required to provide high performance for better user experience. Thereby, Application Processors (APs) equipped in mobile devices consist of a number of out-of-order superscalar cores that execute programs in a high performance. On the other hand, out-of-order cores consume much more power than in-order cores, due to their capability for dynamic scheduling of instructions. Dynamic instruction scheduling requires complex and expensive logics, such as instruction queue and wakeup/select logic. These structures consume more than 40% of total power dissipation of the out-of-order core. To address this problem, we propose Parallel In-Order Execution Architecture by introducing Parallel In-order eXecution Units (PIXU). In our design, ready-to-execute instructions are immediately issued to PIXU without dynamic scheduling but by referring simple table, namely Register Status Table (RST). Our design significantly depletes the wakeup and selection operation counts, which results in the improvement of overall energy efficiency. Consequently, our evaluation shows that our design increases the performance by 13% while reducing energy consumption to 90% with slight area overhead of 3.8% (PIXU: 2.0%, RST: 1.8%) of total area.

International SoC Design Conference (ISOCC)
Ipoom Jeong
Ipoom Jeong
Assistant Professor

My research interests include CPU/GPU microarchitectures, memory/storage system designs, and smart-I/O devices