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Triple-A: Early Operand Collector Allocation for Maximizing GPU Register Bank Utilization
Recent GPUs provisioned with large register files cannot fully utilize the bandwidth between the register files and execution …
Ipoom Jeong, Eunbi Jeong, Nam Sung Kim, Myung Kuk Yoon
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Triple-A: Early Operand Collector Allocation for Maximizing GPU Register Bank Utilization
A Convertible Neural Processor Supporting Adaptive Quantization for Real-Time Neural Networks
This paper presents Stimpack, a responsive approach toward adaptive neural processing unit (NPU), aiming to satisfy service-level …
Hongju Kal, Hyoseong Choi, Ipoom Jeong, Junsung Yang, Won Woo Ro
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LADIO: Leakage-Aware Direct I/O for I/O-Intensive Workloads
This paper presents LADIO (Leakage-Aware Direct I/O), an adaptive direct cache access mechanism (a.k.a., Data Direct I/O, DDIO) to alleviate the inter-I/O (between network I/O and storage I/O) interference problem in modern datacenter servers.
Ipoom Jeong, Jiaqi Lou, Yongseok Son, Yongjoo Park, Yifan Yuan, Nam Sung Kim
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CASH-RF: A Compiler-Assisted Hierarchical Register File in GPUs
Spin-transfer torque magnetic random-access memory (STT-MRAM) is an emerging nonvolatile memory technology that has been received …
Yunho Oh, Ipoom Jeong, Won Woo Ro, Myung Kuk Yoon
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TEA-RC: Thread Context-Aware Register Cache for GPUs
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Ipoom Jeong, Yunho Oh, Won Woo Ro, Myung Kuk Yoon
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OverCome: Coarse-Grained Instruction Commit with Handover Register Renaming
In this paper, we propose an OverCome microarchitecture based on a history-based approach to augment the effective size of the instruction window via coarse-grained instruction commit.
Ipoom Jeong, Changmin Lee, Keunsoo Kim, Won Woo Ro
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OverCome: Coarse-Grained Instruction Commit with Handover Register Renaming