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In this work, we set out to introduce the latest features supported by Intel DSA (Data Streaming Accelerator), deep-dive into its versatility, and analyze its throughput benefits through a comprehensive evaluation.

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In this work, we evaluate true CXL-ready systems based on the latest 4th-generation Intel Xeon CPU with three CXL memory devices from different manufacturers, which divulges important differences between emulated and true CXL memory devices. Based on these observations, we propose a CXL-memory-aware dynamic page allocation policy, Caption, to use CXL memory more efficiently.

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In this work, we propose an energy-efficient microarchitecture named Ballerino, carrying out BALanced and cache-miss toLERable dynamic scheduling via cascaded and clustered IN-Order IQs. The proposed microarchitecture is built upon three key principles that drive dynamic scheduling: instruction readiness, memory/register dependences, and oldest-first selection.