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This work uncovers two previously unknown sources of Last-Level Cache (LLC) contention in Intel Xeon CPUs caused by high-bandwidth I/O devices and proposes A4, a runtime LLC management framework that mitigates these issues. A4 improves performance for latency-sensitive workloads by 51% without significantly affecting low-priority workloads.

This work introduces Universal Predicate Pushdown (UPP), a flexible in-storage processing (ISP) approach that accelerates modern analytical queries by offloading complex filter predicates to FPGA-based storage using a custom instruction set. By efficiently handling diverse operators and data formats, UPP achieves 1.2×–7.9× speedups on Spark queries over a 100 GB TPC-H dataset without requiring changes to input data formats.

The rapid advancements in CPU performance have slowed due to the end of Dennard scaling and the exponential growth of data, making it …

The GPU has been successfully used for diverse emerging compute-intensive applications, including imaging, computer vision, and more …

Virtual memory, with the support of address translation hardware, is a key technique in expanding programmability and memory management …

CXL is the latest interconnect technology built on PCIe, providing three protocols to facilitate three distinct types of devices, each …

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In this work, we set out to introduce the latest features supported by Intel DSA (Data Streaming Accelerator), deep-dive into its versatility, and analyze its throughput benefits through a comprehensive evaluation.