Ipoom Jeong is an Assistant Professor in the Department of System Semiconductor Engineering at Yonsei University and a member of the Institute of Electrical and Electronics Engineers (IEEE). He earned his Ph.D. degree from the Department of Electrical and Electronic Engineering at Yonsei University in 2020. His research expertise encompasses roles such as a Hardware Engineer in the Memory Business division at Samsung Electronics (2020-2021), a Research Professor in the School of Electrical and Electronic Engineering at Yonsei University (2021-2022), and a Postdoctoral Research Associate at the University of Illinois Urbana-Champaign (2022-2024).
PhD in Electrial and Electronic Engineering, 2020
Yonsei University
BS in Electrial and Electronic Engineering, 2014
Yonsei University
In this work, we set out to introduce the latest features supported by Intel DSA (Data Streaming Accelerator), deep-dive into its versatility, and analyze its throughput benefits through a comprehensive evaluation.
In this work, we evaluate true CXL-ready systems based on the latest 4th-generation Intel Xeon CPU with three CXL memory devices from different manufacturers, which divulges important differences between emulated and true CXL memory devices. Based on these observations, we propose a CXL-memory-aware dynamic page allocation policy, Caption, to use CXL memory more efficiently.
In this work, we propose an energy-efficient microarchitecture named Ballerino, carrying out BALanced and cache-miss toLERable dynamic scheduling via cascaded and clustered IN-Order IQs. The proposed microarchitecture is built upon three key principles that drive dynamic scheduling: instruction readiness, memory/register dependences, and oldest-first selection.