Ipoom Jeong is an Assistant Professor in the Department of System Semiconductor Engineering at Yonsei University and a member of the Institute of Electrical and Electronics Engineers (IEEE). He received his Ph.D. in Electrical and Electronic Engineering from Yonsei University in 2020.
His professional experience includes serving as a Hardware Engineer in the Memory Business Division at Samsung Electronics (2020–2021), a Research Professor in the Department of Electrical and Electronic Engineering at Yonsei University (2021–2022), and a Postdoctoral Research Associate at the University of Illinois Urbana-Champaign (2022–2024).
PhD in Electrial and Electronic Engineering, 2020
Yonsei University
BS in Electrial and Electronic Engineering, 2014
Yonsei University
This work uncovers two previously unknown sources of Last-Level Cache (LLC) contention in Intel Xeon CPUs caused by high-bandwidth I/O devices and proposes A4, a runtime LLC management framework that mitigates these issues. A4 improves performance for latency-sensitive workloads by 51% without significantly affecting low-priority workloads.
This work introduces Universal Predicate Pushdown (UPP), a flexible in-storage processing (ISP) approach that accelerates modern analytical queries by offloading complex filter predicates to FPGA-based storage using a custom instruction set. By efficiently handling diverse operators and data formats, UPP achieves 1.2×–7.9× speedups on Spark queries over a 100 GB TPC-H dataset without requiring changes to input data formats.
In this work, we evaluate true CXL-ready systems based on the latest 4th-generation Intel Xeon CPU with three CXL memory devices from different manufacturers, which divulges important differences between emulated and true CXL memory devices. Based on these observations, we propose a CXL-memory-aware dynamic page allocation policy, Caption, to use CXL memory more efficiently.
In this work, we propose an energy-efficient microarchitecture named Ballerino, carrying out BALanced and cache-miss toLERable dynamic scheduling via cascaded and clustered IN-Order IQs. The proposed microarchitecture is built upon three key principles that drive dynamic scheduling: instruction readiness, memory/register dependences, and oldest-first selection.